Power arrays of high voltage devices are commonly used in dc-dc magnetic converters. These high voltage devices are, for instance, implemented as Lateral DMOS (LDMOS) (which is a self-aligned device implemented in a BiCMOS process) or as drain-extended MOS (DeMOS) (which is a non-self-aligned device implemented in a CMOS process). For purposes of this application the term CMOS will be used to also cover BiCMOS. FIG. 1 shows a cross section through a typical NLDMOS-SCR 100, which broadly speaking comprises an LDMOS having one or more p+ regions 102 which are connected to the drain defined by n+ region 104 to provide for double injection of charge carriers. The n+ drain 104 is formed in an n-well or n-drift region 106, which in this case is formed in an n-epitaxial region 108 formed in or on a p-substrate 110. The device 100 further includes an n+ source 114 formed in a p-body or p-well 116, which is formed in the n-epi 108. In this embodiment the NLDMOS SCR 100 further includes a p+ backgate 118 formed in the p-well 116. A polysilicon gate 120, which is formed over a gate oxide 122 and a field oxide (FOX) 124, is provided between the drain contact 130 and source contact 128, this region between the contacts defining the active region. For convenience during fabrication the p+ region 102 may be self aligned with the FOX region 124.
The p+ region 102, n-well or n-drift 106, and p+ region 108 define a parasitic pnp transistor in the NLDMOS-SCR, wherein the base of the parasitic pnp is defined by the n-drift 106. A parasitic npn is in turn defined by the n+ source 114 (which defines the emitter of the parasitic NPN and is typically tied to ground), p-well 116 (which forms the base of the parasitic npn) and n+ drain 104, which forms the collector of the parasitic npn
It will be appreciated that ESD devices have to be designed to tolerate the required dc levels during normal operation as well as the triggering voltage range during an ESD event. In the case of switching or noisy high voltage nodes this creates a problem. Controlling the triggering voltage by dynamically coupling the control electrode of the clamp, e.g. by connecting the gate of an LDSCR clamp 200 to ground through a resistor 202 (as shown in FIG. 2), can cause unpredictable triggering under different loads.
One solution that has been proposed in the past is the use of a fixed voltage reference such as a zener diode 300 to control the control electrode, as shown in FIG. 3. This keeps the triggering voltage consistent under different loads. However, as is shown in FIG. 3, the Zener diode 300 in this example is tied between the switch pad 302 and the gate of the LDSCR 304. Thus the zener 300 is tied to a high voltage and provides its voltage reference to the gate with respect to this high voltage. This solution is suitable for BiCMOS processes where the substrate is isolated with proper HV tolerance, but not for CMOS processes with their low breakdown voltage.
In the case of CMOS processes the breakdown voltage of the Deep n-well or n-epi to p-well is relatively low. For example in the CMOS7-5V 40V and C9T5V processes of the present applicant the breakdown is below 40V. Thus the use of a high side Zener diode as a reference for the gate of the CMOS device would not work.
The present invention seeks to provide a solution to overcome these process limitations.